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I'm guessing the RTL "under the hood" is a single mux but the RTL viewer draws it as one per bit. What are you trying to do? I've never used get_rtl_cells or found a reason to and wonder if there's another way.
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Actually I'm trying to analyze and understand how the rtl view got constructed by the synthes tool.
From above example you can see that my verilog is doing simple demux which after syntheses transformed to one decoder and 4 muxes.
By calling get_rtl_cells I didn't get all instances of the mux, it only gave 1 of them.
Please note that in the cell-id's there are missing 3 id's for those instances:
cell_0
cell_1
cell_2
cell_3
cell_4
Why I'm not getting cell_1.. cell_3? And how the RTL Netlist View tool in the Quartus determines this?
Honored Contributor
