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Terry6's avatar
Terry6
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3 years ago

Generic Quad SPI Controller II IP questions

I have several questions about the Generic Quad SPI Controller II IP. The only documentation I can find on this core is a small section in the Embedded Peripherals User Guide. Is there a document tha...
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi


Sorry for the confusion. Yes you are right. Thanks for raising this up to us.

The behavior is indeed that WEL needs to be manually toggled for Sector Protect, Sector Erase and Bulk Erase.

This behavior will be documented in the document.

We are in the midst of doing the documentation update.


Regards

Jingyang, Teh


  • Terry6's avatar
    Terry6
    Icon for New Contributor rankNew Contributor
    3 years ago

    Thanks for the update and I'm glad that our findings align.

    I would recommend that Intel re-investigate the clock rate (Question #5 in the original post). My sims and FPGA builds show that the design and PROM interface meet timing and behave as expected when the clock rate is 100MHz. Maybe this is only true for Micron PROMs because I have not simulated with Intel PROMs.

    Please consider this support request accepted and closed and thanks again.

    Terry