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Altera_Forum
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Honored ContributorGenerating PWM in cyclon2
Hello
I am trying to write codes to generate PWM pulses in my FPGA, but it seems it does not funtion. The input "rst" reset the program but it does not synchronize with the "rst" input. Can any one help me please!!! entity pwm_out is port( clk : in std_logic; rst : in std_logic; loadin : in std_logic_vector(15 downto 0); pwmout : out std_logic); end entity; architecture pwm_out of pwm_out is signal cnt : std_logic_vector(16 downto 0):= "00000000000000000"; begin process (clk, loadin) begin if (rising_edge(clk)) then if (rst = '1') then cnt <= ("0" & loadin); else if (rst = '0') then cnt <= (cnt+1); end if; end if; end if; end process; pwmout <= cnt(16); end pwm_out;9 Replies
Altera_ForumHi Sameer,
don't know if my suggestions will make your system work. But please make the following changes: --- Quote Start --- entity pwm_out is port( clk : in std_logic; rst : in std_logic; loadin : in std_logic_vector(15 downto 0); pwmout : out std_logic); end entity; architecture pwm_out of pwm_out is signal cnt : std_logic_vector(16 downto 0);-- no initialization possible here, only in testbench begin process (clk) -- this is a clocked process, so "loadin" should be removed begin if (rising_edge(clk)) then if (rst = '1') then cnt <= ("0" & loadin); else if (rst = '0') then cnt <= (cnt+1); end if; end if; end if; end process; pwmout <= cnt(16); end pwm_out; --- Quote End --- The rest of your code looks good!- Altera_Forum
Thanks a lot for your help. I tested the code and it has the same problem. I want the pwm output to be zero until the rst pin goes high, however now, it starts ON/OFF regardless of the rst pin :mad:
- Altera_Forum--- Quote Start --- I want the pwm output to be zero until the rst pin goes high --- Quote End --- But you coded
So it's counting and toggling the output while rst is low. Unfortunately, I don't understand the intended operation and how it's related to PWM.if (rst = '0') then cnt <= (cnt+1); - Altera_Forum
I am very new in FGPA. Basically I am want to generate 20 ms PWM pulse, (18 ms OFF time, 2 ms On time). It seems my approuch is not working.
Any help will be very much appreciated :) - Altera_Forum
To my opinion, writing a code should start with clearly specifying the intended behaviour. That's not specific to HDL programming, but it's also missing in the present case. Also the clock frequency and the expected number format of the involved signals, e.g. loadin should be clarified.
- Altera_Forum
Hi Sameer,
did you solve your problems with the PWM? You have a synchronized reset input. What if you use an asynchronized reset? ... begin process (clk, rst) begin if (rst = '1') then cnt <= ("0" & loadin); elsif (rising_edge(clk)) then cnt <= (cnt+1); ... - Altera_Forum
Dear All,
This is Reza, Actually my basic field is Power Electrical Engineering but in the University I'm studying I have got involve with FPGA. The Research Topic has been given to me is Pulse With Modulation with FPGA and my board is Cyclone II. Could you please help regarding me. How can I start and how can I find the Verilog or VHDL codes. I need a simple PWM project based on Cyclone II after that I think I will be able to understand the process and go ahead. Please kindly help me regarding that. Thank you all. - Altera_Forum
Go to altera website and type PWM in the search bar.
You'll get many results to start with (AN501 is a good one). - Altera_Forum
Thank you pantxoa,
But the example is for PWM with MAX II. My Board is Cyclone II starter development board. I think here are a lot of differences and I can't use the source codes and pin assignment. I'm searching for a very simple project for example changing the brightness of some LEDs by using PWM in Cyclone II. Could you please guide me.
