Generating PWM in cyclon2

Hi Sameer,

don't know if my suggestions will make your system work. But please make the following changes:

--- Quote Start ---

entity pwm_out is

port(

clk : in std_logic;

rst : in std_logic;

loadin : in std_logic_vector(15 downto 0);

pwmout : out std_logic);

end entity;

architecture pwm_out of pwm_out is

signal cnt : std_logic_vector(16 downto 0);-- no initialization possible here, only in testbench

begin

process (clk) -- this is a clocked process, so "loadin" should be removed

begin

if (rising_edge(clk)) then

if (rst = '1') then

cnt <= ("0" & loadin);

else

if (rst = '0') then

cnt <= (cnt+1);

end if;

end if;

end if;

end process;

pwmout <= cnt(16);

end pwm_out;

--- Quote End ---

The rest of your code looks good!