sumanth1New Contributor3 years agoGenerating an Agilex per pin RLC IBIS (.ibs) file Hi, I'm trying to produce an ibis file for my FPGA design using the method outlined in: Generating an Agilex per pin RLC IBIS (.ibs) file (intel.com) I require package-specific RLC data for th...Show More
AqidAyman_AlteraRegular Contributor3 years agoHi,I have emailed you another file.Can you check it?Regards,Aqid
Recent DiscussionsLooking for the Document ID 854068SolvedAbout floating voltage of the Agilex 3 power on resetSuggestion of carry chain type TDC of Cyclone 10 GX FPGA chipsIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAImplementation of lower data rate.