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The platform consists of an evaluation board from Xilinx ML505 (on which there is a Virtex 5)
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This is an Altera group. You'll need to go and find a Xilinx group for device related help.
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which will implement the baseband digital processing and another board (Software Defined Radio) for the analog front end that includes the blocks needed (modulator / demodulator, filter, LNA, PA, local oscillator) to communicate on the UHF band (900 MHz).
The platform requires a 12-bit DAC and an ADC 12-bit to adapt the two boards.
So I need help to generate a baseband signal (VHDL description) with a defined frequency, otherwise, I have trouble to describe the signal generator in VHDL
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The following has references that will help:
http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100paper_hawkins.pdf http://www.ovro.caltech.edu/~dwh/correlator/pdf/esc-100slides_hawkins.pdf Also look at the Xilinx DSP book
http://www.xilinx.com/publications/archives/books/dsp.pdf Cheers,
Dave
Honored Contributor
