Honored ContributorI'm new to FPGA/CPLD. Could any one help me?
I'm wondering if I can use CPLD/FPGA to generate some patterns to output pins? This is for some simple test purpose. For example, under 50MHz clock, to generate pattern as "0011110000111100101010...." As I know, the CPLD/FPGAs are to be programmed as logic functions. Appreciate for the answers.
Honored ContributorI read through the articles and found that it's too difficult to me.
Any starting materials that I can refer to generate serial patterns? Thanks!Honored ContributorHonored ContributorDave,
I learned with the lpmshiftreg mega function but still got problems. I attached the simulation waveform. Basically, the serial output have no response after CLK enabled when d[7..0] was put as data input. Do you know why? Thanks! CliffHonored ContributorHi Cliff,
--- Quote Start --- I learned with the lpmshiftreg mega function but still got problems. I attached the simulation waveform. Basically, the serial output have no response after CLK enabled when d[7..0] was put as data input. Do you know why? --- Quote End --- Can you please upload a testbench for the device. That'll make it clearer whether you are using it correctly. If you need an example testbench to get you started, use the one on this thread: http://www.alteraforum.com/forum/showthread.php?t=32386 Cheers, DaveHonored ContributorHi Dave,
I tried lpmshiftreg in Megafunction of QuarterII and it works finally. Thanks for your patience replying me so many questions. CliffHonored ContributorHi Cliff,
--- Quote Start --- I tried lpmshiftreg in Megafunction of QuarterII and it works finally. --- Quote End --- Great! But take the time to look at the Modelsim simulation example too. Its a very powerful tool, and worth learning. --- Quote Start --- Thanks for your patience replying me so many questions. --- Quote End --- You're welcome. Cheers, Dave
