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Altera_Forum
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14 years ago

Generate patterns through CPLD(MAXII)?

I'm new to FPGA/CPLD. Could any one help me? I'm wondering if I can use CPLD/FPGA to generate some patterns to output pins? This is for some simple test purpose. For example, under 50MHz clo...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Hi Cliff,

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I learned with the lpmshiftreg mega function but still got problems.

I attached the simulation waveform.

Basically, the serial output have no response after CLK enabled when d[7..0] was put as data input.

Do you know why?

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Can you please upload a testbench for the device. That'll make it clearer whether you are using it correctly. If you need an example testbench to get you started, use the one on this thread:

http://www.alteraforum.com/forum/showthread.php?t=32386

Cheers,

Dave