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kaz,
MAXII actually has a LUT-architecture! (see page 2-8 of the MAX II Device Handbook).
ghxy00,
The issue with long counters is that even the fast carry chain tends to take longer. Cascading 8-bit lpm counters using a look-ahead register carry-over to the next counter will generate the fastest counter.
Actually I am working on a StratixII GX EP2SGX60F1152-C3 design where I have trouble with a 24 bit counter running at 100 MHz!
So I amused myself a bit and made a small test-project for a (slower) MAXII EPM240ZM68C7 device (see attached .qar). I got 44.98 MHz for a standard LPM based design, and got 102 Mhz for the cascaded LPM version. This comes of course with a price; you will use more LUTs. Design settings were : Analysis set to Speed and fitting to Standard Effort.
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It's true that more logic elements are used. I have compare two kinds of counters: one 22bit large counter to four 5bit small counter. The used LE are respectively 31 to 28. (please attached source code and summary info files).
Unfortunately, in the design with cascaded counters, the ripple clocks are generated. How to remove such warning?
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