Altera_ForumHonored Contributor15 years agoGenerate 1Hz clock from a 50MHz clock I want to generate 1Hz clock with 50% duty from 40MHZ input clock to MAX II CPLD. I had known to keep the 40MHz clock as input then use the generated 1Hz clk signals from the counter divisions as ...Show More
Altera_ForumHonored Contributor15 years agoOh and count down instead of counting up. It's simpler to detect that underflow.
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