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Altera_Forum
Honored Contributor
Honored ContributorGeneral questions about memories, configuration and FPGA systems.
Hi,
I have done some research on the forum about the topic, but i have still some questions and want to verify and sum up everything. In my questions about system configuration i will refer to Cyclone III device family. 1. Some memories questions: 1a. Regarding SRAM memory for NIOS II code. I have seen people using two chips with 16 buses in parallel giving 32 bit bus. I haven't verified that, but is NIOS II using 32 bit instructions ? So it would be most efficent to use it like that. What about using only one chip ? Does it mean that NIOS would have to read the memory two times - so the code could be executed slower ? Also on this forum couple of people suggested for that not using A0 of the SRAM chip address. I was looking for SRAM chips on digikey with 32 bit data bus already - they are quite expensive. That's why it is better to use two 16 bit chips? 1.b. Is external SRAM memory with 10ns access time really much slower that for example internal on-chip sram with 100 MHz clock? 1c. Regarding FLASH memory. There are two main types of flash NANDs and NORs. As farest i know NAND have to be read/written in a page manner, while NORs can be accessed directly at desired address. Is it always better to use NORs with FPGA? Or is there a purpose for using NANDs? 1d. What about the main difference between SRAM and DRAM ICs. I know that: - SRAM usually has 6 transistors, and DRAM is one MOSFET + capacitor - so it's cheaper. - SRAM doesn't have to be constantly refreshed so it consumes less power. - And last thing that - please correct me if i'm wrong: SRAMs are faster, that's why they used as a cache memory, but ultimately DRAM synchronous clock, bursts allow for higher bandwidth ? 1e.Is with those other memories the same consideration about NIOS 32 bit bus and instructions? 2. System configuration. I have found out that EPCS configuration memories are quite expensive, that's why people usually don't use them, right ? Let's stick for a while with that memory anyway. 2a. I have read Cyclone III documentation regarding configuration. Active Serial is used with EPCS chips. I read the remote configuration part, and it seems that i can store as many configuration files in the epcs as i want. If the time comes i can using NIOS or my custom logic to reconfigure FPGA with a different code, configuration. The documentation suggested that the address for the memory configuration to start with is at the beginning of the EPCS. "When used with configuration memory, remote update mode allows an application configuration to start at any flash sector boundary." Is that correct ? 2b. In the same documentation there was also smth about that configuration memory can mean not only EPCS device but also parallel flash memory. Does it mean that for example instead of using expensive EPCS i could use cheaper NOR flash or what kind of flash ? and that i could have the same functionality, with remote configuration etc. using Active Serial? Ok just right now i have found here http://www.altera.com/support/devices/configuration/cfg-compare.html that it can be used, and it's called AP. And that it needs CFI flash. Any traps here? 2c. Can i in the same CFI Flash memory hold both more conifguration files and the code for NIOS II ? There are some NIos commands like: sof2flash, elf2flash, nios2-configure-sof,nios2-flash-programmer. Using those commands i can put everything that i want in that flash in different address space? It simply needs the pinout for FLASH and it knows how to use it? I can use for the connection FPGA GPIO? 2.d In case of having nios code in the same FLASH, i should simply give NIOS the addres of the beginning of the code for it in FLASH as a Reset Vector. 2.e. I haven't found that out - how is the code then copied to run from SRAM (for faster execution) - Because i can assume that it could be run directly from that flash. 2.f. Before i started to write this post i was thinking about using some microprocessor to program the FPGA using PS or FPP. I wanted to use some FLASH memory to store all different configurations for the FPGA, and mircoprocessor would simply read the FLASH and program the FPGA. I could use UART, USB or any different protocol i can come up with to upgrade for example the FPGA configuration automatically. However FPGA can receive data, reprogram the CFI Flash and reconfigure itself. So correct me if i'm wrong but there is really no need for external uC? ////////////////////////////////// Thanks for any answers to my questions, please address them by points and feel free to write some other stuff that i should consider, read documentation etc. best regards, madness18 Replies
Altera_Forumtl;dr
but for first question: since Nios II is 32bit CPU, then it is much better to use 32bit memory bus. I've tested 16bit and 32bit SDRAM solutions and the 32bit one is way much faster than 16bit... I couldn't achieve more than 100MHz Nios II CPU speed using 16bit memory bus.- Altera_Forum
Hi,
It wasn't that long Socrates :) It's a general discussion part of the forum, so i posted all questions that i have, divided them in related parts, gave them numbers for more clearity - not a bunch of text that would be hard to address. How the instructions read is performed by NIOS in case of 16 bits ? And i'll repeat my last questions, because i would really need to verify that. Could I use CFI Flash for configuring automatically the FPGA and store different configuration codes and when needed start with different one ? Is it possible to store there also the code for NIOS that would be copied to SRAM or SDRAM? How copying is done? best, madness - Altera_Forum--- Quote Start --- Could I use CFI Flash for configuring automatically the FPGA and store different configuration codes and when needed start with different one ? --- Quote End --- AFAIK yes. Check how's the design made on Cyclone III development kit. --- Quote Start --- Is it possible to store there also the code for NIOS that would be copied to SRAM or SDRAM? How copying is done? --- Quote End --- AFAIK yes. You create a small bootloader, which runs from on-chip ram (Your reset vector must point there). Then that bootloader copies data from flash to sram/sdram and jumps to that address.
- Altera_Forum
Thanks Socrates,
Is there anything that i must watch for when choosing DRAMs? For example i have seen that DDR Controllers have a specific memory parts to choose - i was trying to find one on Digikey - even if they are on the list, the stack is 0. Can i buy any memory, and then in DDR Controller choose one memory and adjust timings for the one that i bought? best, - Altera_Forum
What Socrates wrote is correct. I only add some extra info.
Regarding the subject of storing different configurations/Nios-software into flash, you may read Altera application notes AN458 and AN521, or simply search the website for anything related to Remote Update. In case you need to select one of the configurations stored in flash, the way of operation is actually this: FPGA always starts with a base configuration (usually referred to as 'factory'), which is stored at address 0 of configuration device (i.e. epcs or CFI) This is usually a non-fully operational firmware which only purpose is to boot the real application, user selected by means of dip switches, buttons, serial port command or any method you choose. The base configuration sets up the remote update core for a fpga reconfiguration using an image at the desired flash address. Only after this step the actual configuration becomes operational. - Altera_Forum--- Quote Start --- Thanks Socrates, Is there anything that i must watch for when choosing DRAMs? For example i have seen that DDR Controllers have a specific memory parts to choose - i was trying to find one on Digikey - even if they are on the list, the stack is 0. Can i buy any memory, and then in DDR Controller choose one memory and adjust timings for the one that i bought? best, --- Quote End --- Depends on FPGA. SDRAM is the easiest: You can route it to any pins You want, the controller core is really small. DDR and DDR2 is harder, because there are only dedicated pins for DQ/DQS pins and controller cores are damn huge. DDR3 is not supported by Cyclone III.
- Altera_Forum
Regarding the memory width question, You can use a 32, 16 or even 8 bit memory width (this applies SRAM, SDRAM or Flash). But since Nios is 32bits, it will require respectively 1, 2 or 4 memory accesses to fetch a single instruction or data. That's why a 32bit wide device is faster.
Regarding the differences between sram and sdram, you correctly remarked that sram are asynchronous, so they usually require adding wait states in order to meet the timing. This will reduce the throughput compared to sdram, especially in burst. On the other hand sdram are slower in case of random access, because of the cumbersome access method (rows, columns, RAS, CAS, precharge ...) - Altera_Forum
Hi,
thanks you both for the replies. 1. So i can connect CFI Flash, SRAM, SDRAM to any pins that i want. Is there any consideration about using the sam IO bank for the one type of memory ? Or it doesn't matter? 2. Thanks Chris for the application notes, i'll read them both. Does it mean that the base configuration can be rather small containing remote update core, so it gets loaded fast and custom logic can read the FLASH in a specififc address (where is the info about what configuration at what address to load), and then the core would use that info and start the application. I suppose that it wouldnt be much longer than using Passive Serial method? Every new configuration would have to contain also the remote update core, so when the user wants to change the configuration (or simply change the functionality) it could be also be done from the that point. I would have to before reconfiguration write the FLASH memory with the new address for configuration in case of power supply being shut off. 3. Can i choose any specific chip of DDR, DDR2 if i'm able to meet the timing constraints ? I suppose that here would be the best to use the fastest speed grade FPGA for that kind of memory. 4. Cris how will the NIOS know if it has to read the memory for times. Is it smth that can be set in Qsys system ? I have copied this from the forum: "When using external SRAM with 32 bits interface one doesn't use A0 and A1 addresses. When using extrenal SRAM with 16 bits interface one doesn't use A0 bit of the SRAM address." Where and in what cases i should consider such connections? Once again thanks for the replies, best, madness - Altera_Forum
It is also worth pointing out that all read cycles done by the nios cpu assert all 4 byte enables, the unwanted bytes are discarded internally.
Write cycles will assert the 'correct' byte enables. However if a byte write is done to an 8-bit slave the 'fabric' will always generate 4 write cycles - 3 of which will have the (single) byte enable inactive. - Altera_Forum--- Quote Start --- It is also worth pointing out that all read cycles done by the nios cpu assert all 4 byte enables, the unwanted bytes are discarded internally. Write cycles will assert the 'correct' byte enables. However if a byte write is done to an 8-bit slave the 'fabric' will always generate 4 write cycles - 3 of which will have the (single) byte enable inactive. --- Quote End --- Hi Dsl, I don't really understand those memory byte enables. If i wanted to use memory with 16-bits i could really simply tie those to correct values and never use them again ? If i wanted to use the memory with 8-bit data i could use those byte enables to: 1. Select the lower byte - write the data at address 0 2. Select the higher byte - tie the data at address 0 3. Select the lower byte - write the data at address 1 4. Select the higher byte - tie the data at address 1 So it would effectively change the memory organization. But those byte enables are only masks, as i suppose they are only for the reason to not change the higher/lower word when connecting with 16-bit data line. Are normal memory controllers for 8-bit 'fabric' chips as you say, able to use effectively 16-bit memory ? Because those byte enables are only for masking data. When connecting 8 bits to D[0..7] of memory i'm able to write only to lower bytes. Those bytes enables normally are not for routing the data internally in memory chip. So when connecting to 8-bit to 16-bit memory those bytes enables really doesn't matter, right? Are there any other usage for byte enables? The same concept would be in DDR memories? best regards, madness
