General questions about memories, configuration and FPGA systems.

Hi,

thanks you both for the replies.

1. So i can connect CFI Flash, SRAM, SDRAM to any pins that i want.

Is there any consideration about using the sam IO bank for the one type of memory ? Or it doesn't matter?

2. Thanks Chris for the application notes, i'll read them both. Does it mean that the

base configuration can be rather small containing remote update core, so it gets loaded fast and

custom logic can read the FLASH in a specififc address (where is the info about what configuration at what address to load), and then the core would use that info and start the application.

I suppose that it wouldnt be much longer than using Passive Serial method?

Every new configuration would have to contain also the remote update core, so when the user wants to change the configuration (or simply change the functionality) it could be also be done from the that point. I would have to before reconfiguration write the FLASH memory with the new address for configuration in case of power supply being shut off.

3. Can i choose any specific chip of DDR, DDR2 if i'm able to meet the timing constraints ? I suppose that here would be the best to use the fastest speed grade FPGA for that kind of memory.

4. Cris how will the NIOS know if it has to read the memory for times. Is it smth that can be set in Qsys system ?

I have copied this from the forum:

"When using external SRAM with 32 bits interface one doesn't use A0 and A1 addresses.

When using extrenal SRAM with 16 bits interface one doesn't use A0 bit of the SRAM address."

Where and in what cases i should consider such connections?

Once again thanks for the replies,

best,

madness