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Altera_Forum
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16 years ago

gate timing spec on 40nm FPGA

Hi everybody, Does anyone know what is the delay time of a "not" gate in 40nm technology? And does anyone know what is the minimum pulse width for clock input in one FlipFlop or in one D-latc...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Ok, thank you I will try it.

Big thanks for the help.:)

Shalom