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Altera_Forum
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14 years ago

functional simulation + STA = gate level simulation?

Hi: Is "functional simulation" + "STA" = "gate level simulation"? I designed a project,and run the functional simulation successfully,at the same time,the timequest timing analysis has no warnin...
Altera_Forum's avatar
Altera_Forum
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14 years ago

Most people do not do timing/gate sims, just RTL + STA, as you describe. If you're doing funky circuits(non-synchronous and not recommended), timing sims may be helpful. They also might catch an incorrect timing constraint, such as a multicycle that really isn't. In general, STA is better thought since it covers a range of timing, i.e. all timing corners, while the timing simulations only do a specific one.

And in reality, the testing is RTL Sim + STA + Running in FPGA. That last one is key, and why ASIC designers might still do timing sims while FPGA designers usually do not.