Function of MSEL pins in FPGA

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I would like to know, the function of MSEL[2:0] pins on Cyclone-IV.

Will they decide the mode in which the FPGA is getting configured ?

Or the mode in which the EEPROM is getting programmed ?.

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The first answer is the correct one: they select the mode FPGA is getting configured.

JTAG programming ovverrides MSEL pins status, so you can configure through jtag independently from the MSEL wiring.

Same applies to eprom programming which is not affected by msel pins.

Indeed Altera suggests to connect all MSEL pins to gnd whenever only jtag configuration is supposed to be used, but this is only to avoid to let them floating and possibly trigger a configuration attempt from an unexistent device.

If you designed the board to use AS mode when deployed on the field, then you can simply hardwire MSEL pins to select AS mode: you'll still be able to use jtag in the whole design and debug phase and the board will be ready to configure from epcs when you release the firmware.

One add-on...

The information given in the datasheet "JTAG overrides MSEL settings" is true as far as JTAG overrides any *valid* MSEL connection. There were already a few issues discussed here with invalid MSEL combinations (not all 8 possible combinations 000 to 111 are defined in the handbook) prevent any operation even JTAG I/F configuration... w/o correct (defined) combination these devices were not configurable by JTAG. This seems to be caused by Note (2) for Table 8-3 in the Handbook is a little bit misleading... (would be more precise: JTAG takes precedence... which means that the MSEL pin settings - while requied to be set to one of the specified combinations - are ignored)

Thus you either should connect all to GND (being the coding for passive serial) or the combination you intend to use on the board but not to a combination of MSEL and "false" configuration voltage (e.g. 3.3V and 010 for active serial standard for 3V and 2.5V)

BTW: EEPROM programming uses direct interface with EEPROM, tapping DCLK, DATA, ... but no JTAG signals at all..

Dear Carlhermann,

"Thus you either should connect all to GND (being the coding for passive serial) or the combination you intend to use on the board but not to a combination of MSEL and "false" configuration voltage (e.g. 3.3V and 010 for active serial standard for 3V and 2.5V) "

I have not understood the example you given. Does this mean the following....?

Don't connect MSEL pins to '010', if the configuration voltage standard is 3V & 2.5V.

Connect MSEL to 011 if the configuration voltage standard is 3V & 2.5V. Please confirm.

If the above understanding is correct please confirm the following.

I am referring Table 8–5. Configuration Schemes for Cyclone IV E Devices of Cyclone-IV handbook.

The note below the table is copied below.

1) Configuration voltage standard applied to the VCCIO supply of the bank in which the configuration pins reside.

In cyclone-IV E device, all configuration pins(Active serial configuration pins) are in bank 1. I want to configure FPGA in AS mode. I will power bank 1 at 3.3V only.

Will it be alright if I set to MSEL=010 ? Or do I need to consider other configuration pins listed in Table 8–18. Configuration Pin Summary for Cyclone IV E Devices, and their bank voltages to select MSEL values ?

Please help.

Regards,

Thulasi

Hi,

if you're design is using 3.3V VCCIO for bank1 and you want to configure the device via Active Serial, the correct configuration is line 3, MSEL2..0 = 010 as you already wrote.

I assume your design is like Figure 8-6 "in system programming of serial configuration devices".

Note(1) gives you the pull-up voltages to be 3.3VDC

Note(4) references the defnitions for MSEL to be observed with 8-5 for the Cyclone IV E while a logic '1' is a connection to VCCA (which is the PLL analog voltage required anyhow)

Regards