Function of MSEL pins in FPGA

One add-on...

The information given in the datasheet "JTAG overrides MSEL settings" is true as far as JTAG overrides any *valid* MSEL connection. There were already a few issues discussed here with invalid MSEL combinations (not all 8 possible combinations 000 to 111 are defined in the handbook) prevent any operation even JTAG I/F configuration... w/o correct (defined) combination these devices were not configurable by JTAG. This seems to be caused by Note (2) for Table 8-3 in the Handbook is a little bit misleading... (would be more precise: JTAG takes precedence... which means that the MSEL pin settings - while requied to be set to one of the specified combinations - are ignored)

Thus you either should connect all to GND (being the coding for passive serial) or the combination you intend to use on the board but not to a combination of MSEL and "false" configuration voltage (e.g. 3.3V and 010 for active serial standard for 3V and 2.5V)

BTW: EEPROM programming uses direct interface with EEPROM, tapping DCLK, DATA, ... but no JTAG signals at all..