NIOS-II NOR-Flash boot Queries Issues

Dear Altera,

Brian here, and there is a very unclear documentation on consolidation the NIOS-II firmware.

According to "an-736-nios-ii-processor-booting-from-altera-serial-flash-epcq" We are supposed to use serial flash controller II with EPCQ/NOR-Flash variant. While under that document there are no clear mentioning how to deal with CPU speed > 25/50M.

Issue 1: clock feeding > 50M will not work?

Issue 2: What happen if cross-clock is applied and the build setup?

It is understand that cross-clock-bridge can be used but no address span explanations are given to the documentation.

Meantime, with only 50M or 25M global clock  the CPU somehow considered as ultra-slow!

So this documentation or the IP itself become completely kind of unpractical.

Apart from the global clock speed, it is also understand that the limitations are due to the internal oscillation clock speed, which means the IP should provide cross-clock or high<->low clock buffering.

Result: It somehow work on our side but unsure thats the correct procedure as what it should.

Any good full setup steps and procedures would be nice so others can follow w/o any hesitation.

Thanks,

Brian