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I would like to know, the function of MSEL[2:0] pins on Cyclone-IV.
Will they decide the mode in which the FPGA is getting configured ?
Or the mode in which the EEPROM is getting programmed ?.
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The first answer is the correct one: they select the mode FPGA is getting configured.
JTAG programming ovverrides MSEL pins status, so you can configure through jtag independently from the MSEL wiring.
Same applies to eprom programming which is not affected by msel pins.
Indeed Altera suggests to connect all MSEL pins to gnd whenever only jtag configuration is supposed to be used, but this is only to avoid to let them floating and possibly trigger a configuration attempt from an unexistent device.
If you designed the board to use AS mode when deployed on the field, then you can simply hardwire MSEL pins to select AS mode: you'll still be able to use jtag in the whole design and debug phase and the board will be ready to configure from epcs when you release the firmware.
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