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Altera_Forum
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12 years ago

Fun or no fun with Cyclone V Integrated ARM processors?

Hello, the following I have posted on another Forum but haven't receive many responses. So, I am going to post it here. I've been reading about the new Cyclone V and it's integrated ARM proces...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi All,

I have used Cyclone V Soc using its single core (Cortex-A9). It is really fun. When it came to use its second core, I have faced troubles (honestly). The second core does not execute any instruction when the first core send an IPI for task scheduling. Second core is stopped at instruction "S:0xFFFF0100 : LDR sp,[pc,#-164] ; [0xFFFF0064] = 0xFFFFE6A4". So in reality the first core bear all the load. The same code is working fine on i.MX6 on 2 cores. What could be the difference?

P.S.

I am using DS-5.