FSM POR/Reset State on Cyclone 10 LP

This should be trivial, but I've never experienced this issue and I can't seem to solve it! I have a very simple FSM that I use to emulate a switch (given the press of a button). I debounce the button and I detect it's edge -- this is it what drives my state transitions. Now to the issue: even though I have specified the Reset state of my FSM to be the OFF state (1'b0), it is powering up into the ON state (1'b1) and I have to manually hit my reset_n push button to force it into the OFF state. Why is this? I have never had this issue with any other Altera (or Xilinx) FPGAs! (Is it a hardware issue?). I have checked all my signals in SignalTap and the only incorrect signal is "state"... Here is the simple FSM:

 module pb_sensor_emulator(
    input wire clk,
    input wire rst_n,
    
    input wire button_in,
    //output wire sensor_out
    output reg sensor_out
);
    reg sensor_reg;
    
    
    /* debounce & detect edge of button */
    wire button_edge;
    reg button_in_d1;
    reg button_db = 1'b0;
    
    // debounce
    debouncer deb(
        .clk(clk),
        .PB(button_in),
        .PB_state(button_db)
    );    
        
    // detect edge
    always @(posedge clk)
    begin
            button_in_d1<=button_db;
    end
    assign button_edge = button_db & ~button_in_d1;
    /********************************/
    
    /* define states for sensor emulator FSM */
    enum logic {OFF = 1'b0, ON = 1'b1} state, nextstate;
     
    /* state transitions */
    always_ff @(posedge clk or negedge rst_n) 
    begin
        if (!rst_n)
            state <= OFF;
        else
            state <= nextstate;
    end
    
    /* state outputs */
    always_comb 
    begin
        /* set defaults */
        sensor_out = 1'b0;
        /* begin output combinational logic */  
        case(state)
            OFF:
            begin
            end
            
            ON:
            begin
                sensor_out = 1'b1;
            end
        endcase
    end
    
    /* next state logic */   
    always_comb
    begin
        /* default next-state */        
        nextstate = OFF;
        /* begin next-state combinational logic */ 
        case(state)
            
            OFF:
            begin
                if(button_edge)
                    nextstate = ON;
                else
                    nextstate = OFF;
            end
            
            ON:
            begin
                if(button_edge)
                    nextstate = OFF;
                else
                    nextstate = ON;
            end
        endcase
    end
    endmodule