fsm debugging Hi I started to check the fsm on real time and got some strange behaviors. I tried working with SignalTap but I didn't like the way he display the waves and we didn't really get how to work with him. So I went to ModelSim and created a test bench and got the next wave form There is a lot of signals there but I can see that the logic is working, the only problem is that the pwm is not working (the signal in red) and I don't know why. This design works when all the code is in the same file (without components) I had the same thing with the encoder enable nut I succeeded in solving it by giving him a default value of '0'. for another way to look were the program got stuck I used a 7 seg display where at the commands bk,fd - 1,2 the fsm got stuck at state 15 and in the commands rt,lt - 3,4 the fsm got stuck at state 10

I have puted the simulation result at a doc because the gif isn't clear

With components and 'red' values showing in modelsim when I assume you're trying to drive the pwm outputs, this might be multiple drivers. With a glance for this over your file, that's not evident, but might be hidden in your components for your pwm drivers (steer, motion). It's best to simulate first. Don't rely on tools like signal tap except for integration. When you develop a module, simulate it. Better yet, have someone else do it (independent verification). Jerry

I have put a batter simulation sample with

thanks for your replay --- Quote Start --- Better yet, have someone else do it (independent verification). Jerry --- Quote End --- well I have no one to check my design because I started to learn VHDL a few months ago by writing codes to a project I am doing and the people here help me a lot with every question I didn't succeeded on solving by myself , with a book or with Google. should I look in the component for the problem or in the fsm ... has i said before and your answer strengthen my believe that the problem is at the component and not in the fsm because when I put everything in one file it's working ( most of it any way I will solve the rest later on)

The enable signals problem was solved earlier by giving them a reset value in the fsm design ( I guess I forgot) For the pwm signals I have posted another picture of the problem according to the modelsim Do I need to put a flip-flop between internal signal that connects to the real world like in the case of the pwm component (pwm signal ) and the fsm design (M_P_signal,S_P_PWM) In order to synchronized between them?

fsm debuging | Altera Community

33 Replies

Altera_Forum
Honored Contributor
15 years ago
helo again,

I think I found the reason why the robot didn't responed to the commands
Can I inside a component create a constant and caculate its value from generics constans like this:

generic (
DC: time:= 17 ms;
clock_period: time:= 20 ns;
max_pulse: time:= 1 ms;
min_pulse: time:= 2 ms;
);

constant duty_cycle: integer:= DC/clock_period; --850000
constant min_cycle: integer:= min_pulse/clock_period; --50000 constant max_cycle: integer:= max_pulse/clock_period; -- 100000
constant neutral_cycle: integer:= neutral_pulse/clock_period ; --75000

and then ask

if (Counter = duty_cycle) then

I think I can't and that the value of the constant duty_cycle is zero
thougts?
Altera_Forum
Honored Contributor
15 years ago
Hi,
Logic has no concept of time. VHDL can be of type time, but you can't expect anything to happen in logic after some number of ms, ns, etc...

So change all your actions (duty_cycle, min_cycle, neutral_cycle) to be integer counters based on a ms timer count ( this timer count is based on a system clock, which I assume is 50 MHz. Count out ms using timers, then make decisions based on timer values.... you can't compile time into silicon.

I think Tricky brings up a critical point of FPGA / ASIC design. In case this was too subtle:
"Before you simulate, make sure your can synthesize the code."

If you simulate something that can't become logic, it's obviously a waste of time.

Jerry
Altera_Forum
Honored Contributor
15 years ago
I need to think about that because I don't have a synthesize problem I am working on quartus all the time and only in the end before I am checking my code for real I am going to modelsim for simulation.
The piace of pwm code I wrote does works when it stand by himself
and there was no problem in using the time package then.
More over I am still using it in the main entity because temporlly I have solved the problem by adding another port called duty_cycle tothe pwm component and he his calculated by the same generics...
so I still don't see why it's a problem

I can only agree that "logic has no concept of time"

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fsm debuging

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