Frequency of operation of M9K bram

Hi Dave,

Thanks for your quick response :) Appreciate it.

I have attached the file : test_harness.v . I am working on multiported memories. Since I was suggested to connect input and output registers to the RAM {since RAM pins cannot be connected directly to IO pins} I have

1) To reduce the number of IO pins used, have instantiated and connected word-wide shift-registers to only "data inputs" of the RAM.

[ Address inputs are left unconnected since the address comes from the control unit and not from IO pins]

2) Then comes the RAM instance itself. - This is the one which is not being inferred. This module if I synthesise it separately, is inferred as M9K blocks. But now it is implemented in Logic cells.

3) Instances of word-wide registers are connected to the RAM output.

Kindly let me know what I could do so that the RAM infers altsyncram component.