`include "E:/Multiported-Memory-Example-Code/LVT/parameters.v"

module test_harness (
  input wire clock,
  input wire enable,
  input wire sr_in,
  output sr_out
  );
  
  wire `WORD sipo_out_0;
  wire `WORD sipo_out_1;
  
  sipo_shift_register s0 (
  .clk (clock),
  .enable (enable),
  .sr_in (sr_in),
  .sr_out (sipo_out_0)
  ); 
  
  sipo_shift_register s1 (
  .clk (clock),
  .enable (enable),
  .sr_in (sr_in),
  .sr_out (sipo_out_1)
  ); 
  
  wire `WORD ram_out_0;
  wire `WORD ram_out_1;
  wire `WORD ram_out_2;
  wire `WORD ram_out_3;
  
  MEM_2w4r m0 (
  .clock (clock),
  
  .write_addr_0 ( ),
  .write_data_0 (sipo_out_0),
  .write_addr_1 ( ),
  .write_data_1 (sipo_out_1),
  
  .read_addr_0 ( ),
  .read_addr_1 ( ),
  .read_addr_2 ( ),
  .read_addr_3 ( ),
  
  .read_data_0 (ram_out_0),
  .read_data_1 (ram_out_1),
  .read_data_2 (ram_out_2),
  .read_data_3 (ram_out_3)
  );
  
 
  
  wire `WORD reg_out0;
  wire `WORD reg_out1;
  wire `WORD reg_out2;
  wire `WORD reg_out3;
  
  word_register w0 (
  .clock (clock),
  .input_port (ram_out_0),
  .output_port (reg_out0)
  );
  
  word_register w1 (
  .clock (clock),
  .input_port (ram_out_1),
  .output_port (reg_out1)
  );
  
  word_register w2 (
  .clock (clock),
  .input_port (ram_out_2),
  .output_port (reg_out2)
  );
  
  word_register w3 (
  .clock (clock),
  .input_port (ram_out_3),
  .output_port (reg_out3)
  );
  
  assign sr_out = reg_out0 & reg_out1 & reg_out2 & reg_out3;
  
endmodule