Frequency limitation for LAI in Arria 10

Thanks for your response. I am not thinking of signaltap. LAI documentation does not specify a frequency limitation, though it does offer this:

"With the Signal Tap Logic Analyzer, you can acquire data at speeds of over 200 MHz. You can achieve the same acquisition speeds with an external logic analyzer; however, you must consider signal integrity issues."

If I build an I/O cell macro with the IP Parameter Editor, I get a message:

"Altera GPIO supports a maximum interface frequency of 300 MHz."

So that tells me that the GPIOs are good to 300 MHz; I assume this applies to 1.8V LVCMOS, which is what the LAI uses. The truth probably lies somewhere in between, but it is not clear what the I/O frequency limitation really means (does it mean I can't sample at 300 MHz, is 300 MHz the 3 dB point of the frequency response, etc.).

I don't expect PCB and connector SI to be a showstopper.