Occasional ContributorI am planning to use the Logic Analyzer Interface to debug an Arria 10 design; documentation does not provide much in the way of performance specifications.
FPGA internal clock speed is ~300 MHz, meaning toggle rate of the I/Os would be ~150 MHz (I intend to use combinatorial/timing mode only).
Is this plan doomed to failure?
Super ContributorI think it really depends on the capabilities of your external logic analyzer. The LAI simply outputs internal signals to the I/O. Maybe you are thinking about Signal Tap, which does have a maximum supported frequency for sampling of the internal signals (used to be 200 MHz; may be higher for newer devices).
#iwork4intel
Occasional ContributorThanks for your response. I am not thinking of signaltap. LAI documentation does not specify a frequency limitation, though it does offer this:
"With the Signal Tap Logic Analyzer, you can acquire data at speeds of over 200 MHz. You can achieve the same acquisition speeds with an external logic analyzer; however, you must consider signal integrity issues."
If I build an I/O cell macro with the IP Parameter Editor, I get a message:
"Altera GPIO supports a maximum interface frequency of 300 MHz."
So that tells me that the GPIOs are good to 300 MHz; I assume this applies to 1.8V LVCMOS, which is what the LAI uses. The truth probably lies somewhere in between, but it is not clear what the I/O frequency limitation really means (does it mean I can't sample at 300 MHz, is 300 MHz the 3 dB point of the frequency response, etc.).
I don't expect PCB and connector SI to be a showstopper.
Frequent Contributor
