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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

Frequency limitation for LAI in Arria 10

I am planning to use the Logic Analyzer Interface to debug an Arria 10 design; documentation does not provide much in the way of performance specifications. FPGA internal clock speed is ~300 MHz, me...
sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
7 years ago

I think it really depends on the capabilities of your external logic analyzer. The LAI simply outputs internal signals to the I/O. Maybe you are thinking about Signal Tap, which does have a maximum supported frequency for sampling of the internal signals (used to be 200 MHz; may be higher for newer devices).

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