FPGA won't load from flash which contains hardware and NIOS software image

Solved.

The instructions to create a .jic file from a sof and elf file are correct.

It turns out to be a hardware issue. There was a capacitor on the conf_done signal which when we removed, the fpga would boot from flash upon power reset. The capacitor was put in to remove noise from the conf_done because conf_done was used as a trigger to cause a reset to our FPGA. Anyways, it seems the capacitor prevented conf_done from going high fast enough to signal the FPGA that it was finished configuration and cause the FPGA not to boot.