FPGA-to-HPS SDRAM vs. HPS-to-FPGA

I googled around and it sounds like MMAP will create uncacheable mappings if the physical address is above main memory (SDRAM in this case). From the processor perspective 0xC000_0000 is indeed above main memory. So I think the slow access is caused by a bunch of non-cacheable accesses being issued in your case.

Since you are trying to set aside a large region of memory for the FPGA to access it might be more manageable to allocate a large continous memory, map it over to physical memory, and access it used DMAs in the FPGA and cacheable accesses from the processor. I have no clue how to do that but the sofltware folks in this forum probably do. I do know it's possible because that's typically how framebuffers are setup in main memory and that's what the OpenCL drivers do as well when you target SoC devices.