FPGA-to-HPS SDRAM vs. HPS-to-FPGA

I apologize, I'm going to repeat some of what you wrote to make sure I understand what you are saying. I can tell english must not be your primary language :-). No worries though, this helps me talk through it:

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(3) Best will receive video in HPS-onchip RAM (64K-- on FFFF0000) and send to FPGA-onchip through DMA, fast processing and download back ! Write operation on AMBA is very faster rather than reading, "master" will use DMA for send 1 buffer, then signal to "slave" queue, back they swap roles... HPS program is in its DDR, and without FPGA-DDR all may be live !

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So if I am understanding you correctly, neither of the options I provided are the "best" approach. Instead, I should store video in HPS RAM and send it directly to a FIFO on the FPGA for processing. Therefore, the use of the external DDR3 is not needed and the FPGA would just be checking the FIFO and when there is data (read request), start processing (?). Also, the DMA would live on the FPGA fabric, correct? Or is there a way to utilize DMA on the HPS through a driver?

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(4) FPGA-part have "reading" pipe for video -- HPS may write direct to these adresses, data fall into FIFO direct, read-write DDR not need. Working starts on fixed level of FIFO, backpressure may be used. Back FPGA must write data to HPS DDR/RAM and signal to queue in another region, because HPS can't "see" writing operations. The smaller DDR using, the faster all throughput and simpler scheme !

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I think this is just an extension of (3), basically the FPGA would have a FIFO and would be checking the status of the FIFO. When there is video, process. Then write the processed video back to the 64k HPS-onchip RAM (FFFF0000).

Do you have a simple example on how to implement this using (1) Quartus (Qsys) and (2) linux device drivers. Doesn't have to be perfect, I just need some help getting started (esp. with the Linux driver side). I'm starting to understand Qsys a little better, but it is still somewhat of black magic for me.

Thank you!