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Honored Contributor
Honored ContributorFPGA-to-HPS SDRAM vs. HPS-to-FPGA
I'm a relatively new EE (about 5 years EE experience), but I have only a few months of hardware design. I have a design question that I'm hoping someone can shed some light on, teach me a little :-) ...
Altera_ForumHonored Contributor
Honored Contributor(3) Best will receive video in HPS-onchip RAM (64K-- on FFFF0000) and send to FPGA-onchip through DMA, fast processing and download back !
Write operation on AMBA is very faster rather than reading, "master" will use DMA for send 1 buffer, then signal to "slave" queue, back they swap roles... HPS program is in its DDR, and without FPGA-DDR all may be live ! (4) FPGA-part have "reading" pipe for video -- HPS may write direct to these adresses, data fall into FIFO direct, read-write DDR not need. Working starts on fixed level of FIFO, backpressure may be used. Back FPGA must write data to HPS DDR/RAM and signal to queue in another region, because HPS can't "see" writing operations. The smaller DDR using, the faster all throughput and simpler scheme !
