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Altera_Forum's avatar
Altera_Forum
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12 years ago

FPGA to HPS SDRAM Interface

Hi,

I want to use the FPGA to HPS SDRAM Interface, in kind of an Avalon MM Bidirectional 64 Bit. Logic is done, simulation results are as expected. I build the design and loaded it into the SoC, Linux has booted. Everything is fine. Just now I used the System Console to initiate a read request, burst length is 128. Some clocks later readdata changes (0x0 to 0xE3530000E5943028), some other clocks later readdatavalid becomes active for only one clock cycle, nothing more happens. Around this Linux locks/hangs. I have attached a SignalTap screen shot.

Just now I read in the SDRAM Controller Subsystem

http://www.altera.com/literature/hb/cyclone-v/cv_54008.pdf

there is something like memory protection. And registers have to set to enable the FPGA to access the SDRAM. Where can I find more detailed explanations about this, how about an example?

Thank you

Tom

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Yes. When I posted the question I used Quartus 13.0SP1. It hat a bug regarding releasing the FPGA2SDRAM

    Bridge from reset. I had to switch to 13.1.

    Thomas
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi Thomas,

    I wish to use the FPGA2SDRAM bridge in my design, as I am having bandwidth issue accessing memory over the FPGA2HPS bridge. Would you kindly explain what steps are required for the FPGA2SDRAM bridge to work?

    For instance, so far I have enabled FPGA2SDRAM bridge (single port with 256bit bidirectional AvalonMM interface). Then I have connected the Avalon-MM masters to that interface in Qsys. But what's next?

    Appreciate the help.
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Hi mbp2014, Hi Tom,

    I´m also implementing the FPGA2HPS SDRAM Bridge, but have it done with Quartus 13.0sp1 without a problem. @ Tom: Can you explain the bug you had by resetting the bridge in Quartus 13.0sp1? How is this reset performed?

    One issue I found out, is the problem with the ARM TrustZone mechanism. The master in the FPGA fabric has to be a secure master, i.e. in Qsys you have to rightclick on the headings of the overview table, than you can select an additional column. In this column you have to specify whether a Master is working in secure or non-secure mode. Only secure masters can access the whole address range.

    Regards,

    Andi
  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    --- Quote Start ---

    Yes. When I posted the question I used Quartus 13.0SP1. It hat a bug regarding releasing the FPGA2SDRAM

    Bridge from reset. I had to switch to 13.1.

    Thomas

    --- Quote End ---

    So is there any registers to be set before fpga2sdram interface working?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    --- Quote Start ---

    So is there any registers to be set before fpga2sdram interface working?

    --- Quote End ---

    Thanks for this thread. The security comment helped me. So here is my 50cnts in return.

    In the design is a HPS with fpga2sdram interface 0 enabled and two JTAG2AVALON MASTERS.

    1. JTAG mastter to the fpga2hps bridge

    2. JTAG master to the fpga2sdram interface

    The following works in the system console

    get_service_paths master

    set nm_generic_master [lindex [get_service_paths master] <YOUR ID TO JTAG mastter to the fpga2hps bridge>]

    open_service master $nm_generic_master

    set nm_sdram_master [lindex [get_service_paths master] <YOUR ID TO JTAG master to the fpga2sdram interface>]

    open_service master $nm_sdram_master

    # release fpga2sdram port 0 from reset

    master_write_32 $nm_generic_master 0xFFC25080 0x0

    master_write_32 $nm_generic_master 0xFFC25080 0x111

    master_read_32 $nm_generic_master 0xFFC25080 1

    # TEST PEEK and POKE at sdram address 768MB

    set base 0x30000000

    # Read at base address through fpga2hps master

    master_read_32 $nm_generic_master $base 0x8

    master_write_32 $nm_generic_master [expr $base + 0x0] 0xDEADBEEF

    master_read_32 $nm_generic_master $base 0x8

    # Read at base address through sdram controller

    master_read_32 $nm_sdram_master $base 0x8

    master_write_32 $nm_sdram_master [expr $base + 0x0] 0xA51CC0DE

    master_read_32 $nm_sdram_master $base 0x8

    # Read at base address through fpga2hps master

    master_read_32 $nm_generic_master $base 0x8