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Altera_Forum
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12 years ago

FPGA to HPS SDRAM Interface

Hi, I want to use the FPGA to HPS SDRAM Interface, in kind of an Avalon MM Bidirectional 64 Bit. Logic is done, simulation results are as expected. I build the design and loaded it into the SoC...
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Altera_Forum
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11 years ago

Hi mbp2014, Hi Tom,

I´m also implementing the FPGA2HPS SDRAM Bridge, but have it done with Quartus 13.0sp1 without a problem. @ Tom: Can you explain the bug you had by resetting the bridge in Quartus 13.0sp1? How is this reset performed?

One issue I found out, is the problem with the ARM TrustZone mechanism. The master in the FPGA fabric has to be a secure master, i.e. in Qsys you have to rightclick on the headings of the overview table, than you can select an additional column. In this column you have to specify whether a Master is working in secure or non-secure mode. Only secure masters can access the whole address range.

Regards,

Andi