FPGA to HPS SDRAM Interface

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So is there any registers to be set before fpga2sdram interface working?

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Thanks for this thread. The security comment helped me. So here is my 50cnts in return.

In the design is a HPS with fpga2sdram interface 0 enabled and two JTAG2AVALON MASTERS.

1. JTAG mastter to the fpga2hps bridge

2. JTAG master to the fpga2sdram interface

The following works in the system console

get_service_paths master

set nm_generic_master [lindex [get_service_paths master] <YOUR ID TO JTAG mastter to the fpga2hps bridge>]

open_service master $nm_generic_master

set nm_sdram_master [lindex [get_service_paths master] <YOUR ID TO JTAG master to the fpga2sdram interface>]

open_service master $nm_sdram_master

# release fpga2sdram port 0 from reset

master_write_32 $nm_generic_master 0xFFC25080 0x0

master_write_32 $nm_generic_master 0xFFC25080 0x111

master_read_32 $nm_generic_master 0xFFC25080 1

# TEST PEEK and POKE at sdram address 768MB

set base 0x30000000

# Read at base address through fpga2hps master

master_read_32 $nm_generic_master $base 0x8

master_write_32 $nm_generic_master [expr $base + 0x0] 0xDEADBEEF

master_read_32 $nm_generic_master $base 0x8

# Read at base address through sdram controller

master_read_32 $nm_sdram_master $base 0x8

master_write_32 $nm_sdram_master [expr $base + 0x0] 0xA51CC0DE

master_read_32 $nm_sdram_master $base 0x8

# Read at base address through fpga2hps master

master_read_32 $nm_generic_master $base 0x8