FPGA to HPS interrupts

If the GIC was setup for level sensitive interrupts I would expect the code that checks for spurious interrupts would have filtered it out. Unfortunately I'm a hardware engineer so I don't know what to point you at but if you look at the code used by some of the other peripherals in the HPS that use edge sensitive interrupts that might be a good starting point.

By increasing the width of the pulse fixing the issue I suspect the pulse width was too narrow for the edge detector to capture it. Typically edge detectors need a two cycle (or more) pulse width. I think the edge detection occurs after the clock crossing so it would be on the 1/4th MPU clock frequency so I would make sure your pulse width is larger than two MPU clock cycles to ensure it always gets captured. So the GIC might be defaulting to edge sensitive and the problem was the pulse was just being lost. If you had a single cycle pulse and only increased it by a couple of clock cycles then the GIC is probably using edge sensitive interrupts but if you increased the pulse width a lot then it's probably setup for level sensitive.