FPGA to HPS (AXI Slave) address range issue

I hate to answer to myself...

It seems that the hps_0.f2h_axi_slave is expecting 32 bit of address but the external bus to avalon bridge is exposing the address bits to cover the range specified in the UI hence the mismatch.

I edited the tcl file of the peripheral and the verilog source code and is working now.

If someone from Altera is reading the forum I would suggest to change the error message from (0x0..0xffffffff) is outside the master's address range (0x0..0xfffff)

into something more specific. (like address width mismatch between the master and the slave)

Thanks in advance,

A