FPGA SRIO with DSP

In my project,I use FPGA arrie II connected with dsp C6455.They are communicate through rapid io.And I have some questions about them.Hope someone will help me about it.

1.Since the Avalon-MM only support little endian,and the rapid IO support big endian only.So it convert the data with the rapid io controller in the fpga.For example,the data 0x01020304 0x05060708 becomes 0x08070605 0x04030201.Then there is a problem.The dsp doesn't have the same process.When I use the little endian in the dsp.The data in the dsp is just 0x08070605 0x01020304.And it can't be solved to convert the dsp to big endian,because the little endian or big endian is 32bit based.And the transform in the rapid io of fpga is 64bit based.

2.I use the direct I/O.And the fpga can access the ddr2 of the dsp.But the fpga can't access the L2 memory of the dsp.I don't know the reason of it.