FPGA reset asynchronous or synchronous?

There is some dedicated hardware for doing the synchronous clear, but it's in there already. Actually, at least on older architectures, it wasn't a simple AND gate. Instead, something else was done to give the D input priority, so that it wasn't slowed down by the synchronous clear, which an AND gate would do. I don't remember the exact details and don't know if it's still done. It was probably only a 100ps savings to your datapath, but an interesting way to do it.