FPGA remote upgrade question

You probably need some logic on the FPGA that the SPI slave can modify in order to generate the SPI master cycles to the EPCS device.

This probably requires multiple SPI requests from the originating CPU in order to generate a single request to the EPCS device.

If you've set the FPGA's SPI slave so that it is able to generate arbitratrary Avalon master cycles (I don't know if there is a standard logic block for that!) then you can use that to drive the normal avalon slave SPI master interface (an SPI slave like that gives a lot of flexibility and can also make debugging easier as it allows dumps of the fgga state).

The simplest thing is to overwrite the main image at the start of the EPCS device and then hard reset the board.

If it all goes horribly wrong you have a 'return to factory' problem for the JTAG rewrite of the EPCS.

There is an optional logic block that will allow a second image to be loaded under 'software' control - some recent threads talk aboit some issues with it (probably trying to boot nios cpus).