FPGA power managment

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Hi,

I have an custom cyclone Iv board. I want to manage power consumption in my board. one idea is to turn off my fpga when i do not need it. but i have a problem with this idea that it is configuration time of FPGA (at least 250 msec) when i used epcs 16 configuration device in the AP mode.

do you have any idea to speed up FPGA configuration or to lower FPGA power without repeat configuration ? whether speed of FPGA configuration can be different when I program it by nios II flash programmer ?

Regards

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if you stop the clock in which case your clock will need gating at source and poses timing problems.

You mention an EPCS16. Can I assume this is connected in as mode - not AP as you wrote? Configuration time of 250ms suggests AS.

It's a board change but you could use AP configuration - much faster than AS. Look at the AP Configuration section, page 8-21, in the configuration and remote system upgrades in cyclone iv devices (https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-iv/cyiv-51008.pdf) section of the handbook. Look at the configuration time equation 8-5 on page 8-30.

You could choose to stop one (or more) clock(s). That will drop the power consumption dramatically. As Kaz say, be careful of your timing.

Cheers,

Alex

Hi,

Yes i modify my mistake to AS mode. Many thanks for your guidance.