FPGA power managment

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Hi,

I have an custom cyclone Iv board. I want to manage power consumption in my board. one idea is to turn off my fpga when i do not need it. but i have a problem with this idea that it is configuration time of FPGA (at least 250 msec) when i used epcs 16 configuration device in the AP mode.

do you have any idea to speed up FPGA configuration or to lower FPGA power without repeat configuration ? whether speed of FPGA configuration can be different when I program it by nios II flash programmer ?

Regards

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if you stop the clock in which case your clock will need gating at source and poses timing problems.