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Altera_Forum
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11 years ago

FPGA partial reconfiguration granularity

excuse me. in altera PR user guider, it usually specified one column to be the Partial reconfiguration region?

could I ask you a question, what is the minimum granularity in the board? Is one whole column or other?

Thank you for your reply

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    This is a very good question and it would be nice that one of the gurus reply.

    Is it possible to reconfigure a single frame or the finest granularity is one column ?

    In addition, while a part of a column is being partially reconfigured does the rest of it keep its functionality taking into account that the entire column has to be reconfigured ?

    Cheers,

    Stef
  • Altera_Forum's avatar
    Altera_Forum
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    Hi! I'll try again. Is it possible that Altera does not have support for PR ? It is a very important topic nowadays and I wouldn't like to change to Xilinx since I like other features a lot.

    Some guru should be able to provide some support here and answer our questions.

    Hope to hear from you soon.

    Cheers,

    Stef
  • Altera_Forum's avatar
    Altera_Forum
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    Hello,

    there is dynamic partial reconfiguration at least in the Stratix V devices. About the other boards, there's not much info around the internet. You can define partial reconfiguration regions as being any LogicLock region afaik.

    The configuration happens column-wise. In other words, even if your PR region is as small as 3x3 wide, the partial bitstream would still comprise at least 1 or 2 vertical passages on the so-called CRAM frames (http://quartushelp.altera.com/14.0/mergedprojects/comp/comp/comp_about_part_reconfig.htm). There's not much info about what actually comprises a CRAM frame though and it would be interesting to know, since the number of CRAM frames inside a partial bitstream directly affects the bitstream size and reconfiguration time.
  • Altera_Forum's avatar
    Altera_Forum
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    Hi comododragon,

    Thanks for the post. Yes, I know that Altera FPGA can be reconfigured, actually I managed to design something partially reconfigurable but my question is about the granularity.

    I am sure that in a column (vertical passage as you called it) there are more than 1 frame. That's why I asked whether it is possible to reconfigure a single frame like in Xilinx FPGAs or the smallest portion is 1 vertical column. I'd like to change only few CRAM bits within a single frame and not the entire column.
  • Altera_Forum's avatar
    Altera_Forum
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    Ok, I think we (or just me) are having some naming confusion here. I understand a column as being a single column of LABs or DSPs or memory cells, etc. I understand a CRAM frame as being composed of one or more (here's the catch, I don't know this quantity) of these columns. Anyone that has better understanding about this should take a look on our discussion.

    What I know is that independent of your logiclock size, the partial bitstream is always a multiple of CRAM frames, with the size and reconf. time depending on which mode you use for your bitstream (SCRUB for non-vertically-overlapping PR regions but half the size, or AND/OR for vertically-overlapping PR regions). In other words, there's no way of reconfiguring just a portion of a CRAM frame. I've understood this from the Partial Reconfiguration Online Course available @ Altera's website.

    Please anyone correct me if I'm wrong, I've entered this PR world this month :P
  • Altera_Forum's avatar
    Altera_Forum
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    Sorry, OF COURSE there's a way to reconfigure just a portion of a CRAM frame, but the bitstream will always comprise CRAM frames as wholes, considering both static and PR region within the frames (it'll ignore messing on static regions and it'll clear-and-set pr region).

  • Altera_Forum's avatar
    Altera_Forum
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    You are right! We should first define some things:

    - column : single column of LABs or DSPs or memory cells... I agree. A vertical column that can be seen in ChipPlanner.

    - frame : A subset of a column, i.e. a column is composed of 20+ frames which cannot be seen ChipPlanner. Not documented. In Xilinx FPGAs each column is composed of several frames. In addition, it is the smallest granularity that can be reconfigured.

    I watched the online course as well and nothing has been said about the frames. It seems that one can only reconfigure an entire column in 2 modes you mentioned and not a part of it, ie. a frame.
  • Altera_Forum's avatar
    Altera_Forum
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    Ok, that's the opposite of what I thought. I thought that one frame was composed of many columns. Nevertheless, this is a very obfuscated field and it'd be nice to have some more info about it, at least how many frames are inside a column and/or how many compose a Stratix V, for example.

  • Altera_Forum's avatar
    Altera_Forum
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    Exactly. That's why I reactivated this thread since it is a hot topic and Altera has to provide more information since in my opinion they are getting better and better!