FPGA partial reconfiguration granularity

Hello,

there is dynamic partial reconfiguration at least in the Stratix V devices. About the other boards, there's not much info around the internet. You can define partial reconfiguration regions as being any LogicLock region afaik.

The configuration happens column-wise. In other words, even if your PR region is as small as 3x3 wide, the partial bitstream would still comprise at least 1 or 2 vertical passages on the so-called CRAM frames (http://quartushelp.altera.com/14.0/mergedprojects/comp/comp/comp_about_part_reconfig.htm). There's not much info about what actually comprises a CRAM frame though and it would be interesting to know, since the number of CRAM frames inside a partial bitstream directly affects the bitstream size and reconfiguration time.