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CSegu's avatar
CSegu
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7 years ago
Solved

FPGA not launching configuration from EPCQ128A device.

On powering up the Cyclone V GX FPGA device, it is not resetting automatically so to be configured from EPCQ128A device. I have set internal oscillator to 12MHz but still it is not launching the configuration file from EPCQ128 which has been programmed with .jic file. Is there any global reset pin ? how to initialize FPGA from EPCQ128A device automatically ?

Thanks.

  • Nooraini_Y_Intel's avatar
    Nooraini_Y_Intel
    7 years ago

    Hi CSegu,

    Happy New Year to you. Which Quartus Prime version are you using to generate the .jic file for EPCQ128A? The Quartus Convert Programming File setting screen shot that you provided was set to EPCQ128 which is a different flash from EPCQ128A device. In AN822 document has mentioned the EPCQA flash device are supported starting from Quartus Prime Standard v17.1. Thus you should be using Quartus Prime Standard v17.1 above to generate the correct programming files for EPCQ128A device.

    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an822.pdf

    Regards,

    Nooraini

10 Replies

  • Nooraini_Y_Intel's avatar
    Nooraini_Y_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hi CSegu,

    Apologize for the delay as most of our agents are out of office due to the year end holidays. Thus please do expect some delay in response.

    What is the nCONFIG, nSTATUS and CONF_DONE singal state after power up? Is the nSTATUS signal stay high all the time after nCONFIG goes high? Or did the nSTATUS signal toggle? Please check on these configuration signals after power.

    Did you set the configuration scheme to Active Serial mode in the Device and Pin option in the Quartus project design before compilation? How did you generate the .jic file? Please provide the steps or the screen shots showing the steps.

    Regards,

    Nooraini

  • CSegu's avatar
    CSegu
    Icon for New Contributor rankNew Contributor
    7 years ago
    Dear Noorani, After power-up the status of the following FPGA pins is the following. Note that before power up the FPGA the EPCQ128 device was programmed satisfactorily with .jic file as shown in attachment Procedure.png. Note that a 10k pull-up resistor to 3.3V is used for each pin as per attachment Scehmatic.png nConfig-> High (3.3V) nStatus-> keeps Toggling Low-High (0 - 3.3V), For how long it should toggle ? CONF_Done->Low (0V) From the above measurements it seems that the nStatus signal keeps toggling after nConfig goes high. What does it mean ? Why ? Is this a problem? if so how can be resolved? Are there any more settings to be done from Quartus IDE ? I have set the configuration scheme to Active Serial as shown in attachments procedure.png and QuartusSettings.png. Kindly let me know in case of more queries. Thank you again for your guidelines. Regards, Clive Seguna
  • Nooraini_Y_Intel's avatar
    Nooraini_Y_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hi CSegu,

    I'm not seeing this Procedure.png and QuartusSettings.png file to see the Quartus settings and steps you did to generate the .jic file. Thus please re-attached both the Procedure.png and QuartusSettings.png screen shot. If the nSTATUS keeps toggling, possible bitstream corruption during the configuration process after power up. The nCONFIG and nSTATUS needs to stay high during the AS configuration process, once all the bitstream is successfully transfer into the FPGA, the CONF_DONE will go high.

    Are you trying to perform ASx4 mode or ASx1 mode? Is the EPCQ128A is connected to the Cyclone V for ASx1 or ASx4 mode? If the ASx4 mode failed then try to change Active Serialx1 mode in the Device and Pin option in the Quartus project design can recompile to get new .sof file. Generate a new .jic and program it into the flash device and monitor if the configuration still fail (CONF_DONE low) or successful (CONF_DONE high).

    Regards,

    Nooraini

  • CSegu's avatar
    CSegu
    Icon for New Contributor rankNew Contributor
    7 years ago
    Dear NYusof, Attached are the images Procedure.png and QuartusSettings showing settings for generating .jic file. I am using ASx1 with EPCQ128A. Why should bitstream be corrupted if I am able to successfully program FPGA via .sof file and JTAG ? How can I remove this corruption? Thanks, Regards, Clive
  • Nooraini_Y_Intel's avatar
    Nooraini_Y_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    7 years ago

    Hi Clive,

    I'm still not seeing any attachment. Again please attached the screen shots. Please do not be confuse between JTAG and AS configuration mode. Programming .sof file via JTAG pins direct to FPGA is different from EPCQA device transferring data into FPGA via ASMI pins (DCLK, nCSO, DATA pins) protocol. Did you set Active Serialx1 mode in the Device and Pin option in the Quartus project design before compilation? Please scope the DCLK, nCSO, DATA0 and DATA pins when power up. Check if those signals are clean(any noise) or not.

    Regards,

    Nooraini

    • CSegu's avatar
      CSegu
      Icon for New Contributor rankNew Contributor
      7 years ago

      Dear Nooraini,

      I have attached files via email. Now I am attaching them again here. Yes I know that JTAG is different from ASx1. I have set ASx1 also in Device Pin options.

      Thank you for your help.

      Regards,

      Clive

      • CSegu's avatar
        CSegu
        Icon for New Contributor rankNew Contributor
        7 years ago
        posted a file.
  • CSegu's avatar
    CSegu
    Icon for New Contributor rankNew Contributor
    7 years ago
    Dear Nooraini,, You were right. I was using incorrect Quartus version. Now the full chain is working. Well done! Thank you. Regards, Clive