FPGA IO sampling rate

You will need to think separately about io toggle rate and io speed(sampling).

Toggle rate depends on many factors and is usually way too fast and may be available in data sheet.

here is an excerpt from altera doc:

"I/O toggle rates vary based on speed grade, loading, and I/O bank location—top/bottom versus left/right. This toggle rate is also a function of the termination used (OCT or external termination) and other settings such as drive strength and slew rate."

io speed is meant to be sampling speed at io register(one clock edge sampling or both using two registers). This is what we should mean by "read" or "write". Fmax at io register depends on device and design constraints mostly and only the timing tool can best tell.

Toggle rate may at times restrict fmax and then timing report will tell under "restricted fmax", however I can guess that the tool can't detect issues like loading and external termination and hence a bad design may violate toggle rate without report from tool.