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Altera_Forum's avatar
Altera_Forum
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17 years ago

FPGA input clock and DDR2

Currently my design has a very high speed DAC providing the system clock to my Stratix II on the top of the FPGA (CLK12p/n) at 1.8V LVDS. Currently my DDR2 is on the bottom of the FPGA. I am currently using a PLL to provide the 250MHZ clock to the entire system, including the DDR2 controller built using the Megawizard. I don't think I'm providing the clock correctly to the DDR2 because I'm getting an error using TimeQuest that says it can't match the DDR2 clock input with an input pin. Any suggestions? Problem is that the top of the FPGA is at 1.8V while the bottom is at 3.3V for the DDR2 SDRAM so I can't simply just move the DDR2 SDRAM to the top of the part.

Any help would be greatly appreciated.

Thanks!

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    First ,LVDS specification is 2.5 and only support on the row bank ; second , the specification of DDR2 is 1.8V SSTL-18 class1&class2 , and both the top and the bottom bank can support DDR2 connection . I think you should check your hardware schematic and refer to the handbook .