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Altera_Forum
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16 years ago

FPGA input clock and DDR2

Currently my design has a very high speed DAC providing the system clock to my Stratix II on the top of the FPGA (CLK12p/n) at 1.8V LVDS. Currently my DDR2 is on the bottom of the FPGA. I am current...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

First ,LVDS specification is 2.5 and only support on the row bank ; second , the specification of DDR2 is 1.8V SSTL-18 class1&class2 , and both the top and the bottom bank can support DDR2 connection . I think you should check your hardware schematic and refer to the handbook .