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AngelVillanueva's avatar
AngelVillanueva
Icon for New Contributor rankNew Contributor
2 years ago

FPGA Initialization / Reset

Hi,

I have tried to search for information on how to manage FPGA initialization / reset and have not found conclusive information so I would appreciate some help on this topic.

- Is it a reset signal always necessary to initialize the FPGA to a known state? What can be done if there is no reset signal available?

- Can you know the initialization value of registers and state machines without using a reset signal?

- Can registers and finite state machines be initialized using VHDL / Verilog code?

Thank you in advance.

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  • Nurina's avatar
    Nurina
    Icon for Regular Contributor rankRegular Contributor
    2 years ago

    Hi,


    We do not receive any response from you on the previous question/reply/answer provided. Please login to https://supporttickets.intel.com , view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


    p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution, give Kudos and rate 4/5 survey


    Regards,

    Nurina