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AngelVillanueva's avatar
AngelVillanueva
Icon for New Contributor rankNew Contributor
2 years ago

FPGA Initialization / Reset

Hi, I have tried to search for information on how to manage FPGA initialization / reset and have not found conclusive information so I would appreciate some help on this topic. - Is it a reset ...
Nurina's avatar
Nurina
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,


As far as I know, it is always necessary to use reset signal to guarantee FPGA initialization in a known state.


Have you tried your dummy code without any RESET signal? What would happen?

Also, normal practise is to use reset = 1 to enable the reset signal. Have you tried this way instead?


Regards,

Nurina


  • _AK6DN_'s avatar
    _AK6DN_
    Icon for Frequent Contributor rankFrequent Contributor
    2 years ago

    "As far as I know, it is always necessary to use reset signal to guarantee FPGA initialization in a known state. "

    Not true. After configuration each and every logic register in the FPGA will be set to a known initial state, as defined in the loaded image.

    The main use of the external reset line is to be able, via some external logic, to force the FPGA into the defined reset condition after it has been powered on and running.