FPGA Initialization / Reset

Thank you for your response.

In this application, I need to be able to reconfigure the FPGA in case of CRAM error due to SEU failure.

I cannot manage the reset signal with power rail monitors since a SEU failure can happen with the power supplies fully stabilized.

I am evaluating using the CONF_DONE or INIT_DONE signals.

• CONF_DONE: As a status output, the CONF_DONE pin drives low before and during configuration. After all configuration data is received without error and the initialization cycle starts, the CONF_DONE pin is released. As a status input, the CONF_DONE pin goes high after all data is received. Then the device initializes and enters user mode. This pin is not available as a user I/O pin.
• INIT_DONE: This is a dual-purpose pin and can be used as an I/O pin when not enabled as an INIT_DONE pin in the Quartus II software. When this pin is enabled, a transition from low to high on the pin indicates that the device has entered user mode. If the INIT_DONE output pin option is enabled in the Quartus II software, the INIT_DONE pin cannot be used as a user I/O pin after configuration.

However, it is important for me to clarify if it is always necessary a hardware reset signal or there are others ways to guarantee FPGA initialization in a known state.