FPGA image booting and NioS system booting

Hi,

Can try Nios II Processor Booting from CFI Flash if using Cyclone V check this https://www.intel.com/content/www/us/en/docs/programmable/683689/current/processor-booting-from-cfi-flash.html

Then probably can set the configuration scheme and mode to passive serial as The PFL IP core allows you to configure the FPGA in passive serial (PS) or fast passive parallel (FPP) scheme. Check this https://www.intel.com/content/www/us/en/docs/programmable/683698/21-1-19-1-0/supported-schemes-and-features.html

Pointing both reset vector and exception vector to Parallel Flash and External RAM (DDR) respectively.

Here are some references may be helpful to you:

https://community.intel.com/t5/FPGA-Wiki/Nios-II-Booting-From-CFI/ta-p/735490

https://malt.zendesk.com/hc/ja/articles/900006257703-Nios-II-Boot-Option-CFI-Flash-

Best Regards,

Sheng

p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.